Title Dr. First Name Harsupreet Last Name Kaur
Designation Professor
Department Department of Electronics Science SDC
Email harsupreetkaur@gmail.com
Webpage
Phone.no 011-24157199
Employement Info
Employee Type Nature Of Employment
Teaching Permanent
Educational Qualifications
Degree/Certification Name Institution Year of Completion
Ph.D. - Ph.D. Electronic Science University of Delhi 2008
UG University of Delhi 2001
PG University of Delhi
Teaching Experience (Within Institution)
Designation Duration
Lecturer 16-08-2007 To 09-08-2009 (1 years, 11 months, 24 days)
Lecturer/ Assistant Professor 11-08-2009 To 20-06-2011 (1 years, 10 months, 9 days)
Assistant Professor 21-07-2011 To 01-04-2013 (1 years, 8 months, 11 days)
Assistant Professor 01-04-2013 To 07-04-2021 (8 years, 6 days)
Associate Professor 08-04-2021 To 28-03-2023 (1 years, 11 months, 20 days)
Research Supervision Overview
PhD Scholars Supervised PhD Degrees Awarded Theses Submitted
3 2 0
Research Publications
Title of Article Type of Publication Name of Journal ISSN Journal Volume Year Link to Article DOI (Digital Object Identifier)
Implementation of source extended multiple field plates and asymmetric doping on β-Ga2O3 MOSFET for high power applications Research Papers in Scopus Listed Journals Micro and Nanostructures 2773-0131 184 https://doi.org/10.1016/j.micrna.2023.207693
Assessing the impact of step gate oxide and gate electrode engineering on performance of β-Ga2O3 MOSFET for high frequency applications Research Papers in Scopus Listed Journals Micro and Nanostructures 2773-0131 180 https://doi.org/10.1016/j.micrna.2023.207603
Exploring the efficacy of implementing field plate design with air gap on β-Ga2O3 MOSFET for high power & RF applications Research Papers in Peer Reviewed Journals Micro and Nanostructures 0749-6036 173 10.1016/j.micrna.2022.207454
Impact of Dual Material Gate Design and Retrograde Channel Doping on β-Ga2O3 MOSFET for High Power and RF Applications Research Papers in Peer Reviewed Journals Silicon 1876-990X 10.1007/s12633-022-02079-7
Exploring the performance of palladium gated – SiGe channel – Polarity controllable–FET for hydrogen gas monitoring applications Research Papers in Peer Reviewed Journals Micro and Nanostructures 0749-6036 169 10.1016/j.micrna.2022.207357
Performance investigation of Reconfigurable–FET under the influence of parameter variability of ferroelectric gate stack at high temperatures Research Papers in Peer Reviewed Journals Microelectronics Journal 0026-2692 124 10.1016/j.mejo.2022.105442
A comprehensive physics based surface potential and drain current model for SiGe channel dual programmable FETs Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 37 10.1088/1361-6641/ac5fdc
Implementing variable doping and work function engineering in β-Ga2O3 MOSFET to realize high breakdown voltage and PfoM Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 37 10.1088/1361-6641/ac5843
Performance and Sensitivity Analysis of Polarity Controllable-Ion Sensitive FET for pH Sensing Applications Research Papers in Peer Reviewed Journals Silicon 1876-990X 14 10.1007/s12633-022-01658-y
Effect of ferroelectric parameters variation on the characteristics of polarity controllable–ferroelectric–field-effect transistors at elevated temperatures Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 35 10.1088/1361-6641/abb9fd
Improved Temperature Resilience and Device Performance of Negative Capacitance Reconfigurable Field Effect Transistors Research Papers in Peer Reviewed Journals IEEE Transactions on Electron Devices 0018-9383 67 10.1109/TED.2019.2961876
Device and Circuit Level Analysis of Negative Capacitance Hybrid CMOS: A Prospect for Low Power/Low Voltage Applications Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 35 10.1088/1361-6641/ab57b4
Performance Assessment of Symmetric Double Gate Negative Capacitance Junctionless Transistor with High-k Spacer at Elevated Temperatures Research Papers in Peer Reviewed Journals Advances in Natural Sciences: Nanoscience and Nanotechnology 2043-6262 10
Superior Performance and Reliability of Double Gate Gaussian Doped Negative Capacitance Junctionless Transistor for 200–500 K Research Papers in Peer Reviewed Journals IETE Technical Review 0256-4602 37 10.1080/02564602.2019.1642149
Study on Impact of Parasitic Capacitance on Performance of Graded Channel Negative Capacitance SOI FET at High Temperature Research Papers in Peer Reviewed Journals IEEE Transactions on Electron Devices 0018-9383 66 10.1109/TED.2019.2917775
Subthreshold Analytical Model for Dual-Material Double Gate Ferroelectric Field Effect Transistor (DMGFeFET) Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 34 10.1088/1361-6641/ab194d
Analysis of Negative-Capacitance Germanium FinFET With the Presence of Fixed Trap Charges Research Papers in Peer Reviewed Journals IEEE Transactions on Electron Devices 0018-9383 66 10.1109/TED.2019.2897637
An analytical subthreshold current model for ferroelectric SiGe-on-insulator field effect transistor (FSGOIFET) Research Papers in Peer Reviewed Journals Semiconductor Science and Technology 0268-1242 34 10.1088/1361-6641/aaf2e6
Impact of Gaussian Doping Profile and Negative Capacitance Effect on Double Gate Junctionless Transistors (DGJLT) Research Papers in Peer Reviewed Journals IEEE Transactions on Electron Devices 0018-9383 65 10.1109/TED.2018.2832843
Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges Research Papers in Peer Reviewed Journals Superlattices and Microstructures 0749-6036 117 https://doi.org/10.1016/j.spmi.2018.03.001
Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors Research Papers in Peer Reviewed Journals Superlattices and Microstructures 0749-6036 111 https://doi.org/10.1016/j.spmi.2017.06.032
High temperature performance of Si:HfO2 based long channel Double Gate Ferroelectric Junctionless Transistors Research Papers in Peer Reviewed Journals Superlattices and Microstructures 0749-6036 103 https://doi.org/10.1016/j.spmi.2017.01.009
Modeling and simulation study of novel Double Gate Ferroelectric Junctionless (DGFJL) transistor Research Papers in Peer Reviewed Journals Superlattices and Microstructures 0749-6036 97 https://doi.org/10.1016/j.spmi.2016.07.024
Impact of Laterally Asymmetric Channel and Gate Stack Design on Device Performance of Surrounding Gate MOSFETs : A Modeling and Simulation Study Research Papers in Peer Reviewed Journals Microwave and Optical Technology Letters 0895-2477 52 https://doi.org/10.1002/mop.25022
An Analytical Threshold Voltage Model for Graded Channel Asymmetric Gate Stack (GCASYMGAS) Surrounding Gate MOSFET Research Papers in Peer Reviewed Journals Solid-state electronics 0038-1101 52 https://doi.org/10.1016/j.sse.2007.09.006
Temperature Dependent Analytical Model of sub-micron GaN MESFETs for Microwave frequency Applications Research Papers in Peer Reviewed Journals Solid-state electronics 0038-1101 52 https://doi.org/10.1016/j.sse.2007.06.010
A Semi-Empirical Model for Admittance and Scattering Parameters of GaN MESFET for microwave circuit applications Research Papers in Peer Reviewed Journals Microwave and optical technology Letters 0895-2477 49
Two Dimensional Subthreshold Analysis of Sub-Micron GaN MESFET Research Papers in Peer Reviewed Journals Microelectronics Journal 0026-2692 38 https://doi.org/10.1016/j.mejo.2007.03.006
Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability Research Papers in Peer Reviewed Journals Solid-state electronics 51 https://doi.org/10.1016/j.sse.2007.01.025
An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET Research Papers in Peer Reviewed Journals Microelectronics Journal 0026-2692 38 https://doi.org/10.1016/j.mejo.2007.01.003
An analytical model for GaN MESFET's using new velocity‐field dependence Research Papers in Peer Reviewed Journals physica status solidi c 1610-1642 3 https://doi.org/10.1002/pssc.200565318
A semi empirical approach for submicron GaN MESFET using an accurate velocity field relationship for high power applications Research Papers in Peer Reviewed Journals Microelectronics Journal 37 https://doi.org/10.1016/j.mejo.2005.09.018
Professional Development Programmes
Programme Title Sponsoring Institution Organizing Institution Role Type of Programme
FDP on “Academic Administration” Teaching Learning Centre, Ramanujan College, under the aegis of Ministry of Education, Pt. Madan Mohan Malyiya National Mission on Teachers & Teaching Attending Faculty Development Programmes
Two weeks National Interdisciplinary Refresher course on Research Methodology and Data Analysis Teaching Learning Centre, Ramanujan College, under the aegis of Ministry of Education, Pt. Madan Mohan Malyiya National Mission on Teachers & Teaching Attending Refresher Program
E-learning and Developing MOOCs for Teaching Process in Higher Education Dept. of Statistics& IQAC, Hindu College in association with Pt. Madan Mohan Malyiya National Mission on Teachers & Teaching Learning Centre, Ramanujan College Attending Faculty Development Programmes
Orientation Programme (OR-61) CPDHE, Delhi Universiy Attending Orientation Programme
Refresher course in Physics Academic Staff Collge, JNU Attending Refresher Program
Honors and Awards
Name of the Award Awarding Body Award Category Level Award Date
Young Scientist Award International Union of Radio Science (Union Radio-Scientifique Internationale) Research International 08-08-2008
Talk Poster Presented
Name of the Activity Role Date of Activity
Delivered Six lectures on VHDL and its applications organized by Department of Electronics, Jammu University Invited Talk 02-04-2022
Gaussian Doped Negative Capacitance Junctionless Transistors - Emerging Prospect for High Temperature Applications Invited Talk 21-05-2022
“Negative Capacitance FETs – Emerging Prospect for Ultra Low Power Applications” Invited Talk 31-05-2021
“Ferroelectric Negative Capacitance Junctionless Transistors For Ultra Low Power Applications” Invited Talk 09-05-2021
“Semiconductor Technology – Innovations, Current Trends and Challenges” Invited Talk 02-12-2020
Emerging Nanoelectronic Devices Invited Talk 20-02-2019
CMOS and VLSI Technology Invited Talk 26-09-2017
CMOS Scaling : Review and Perspectives Invited Talk 02-09-2016
Material and Device Architecture Innovations for Advanced CMOS Technology Invited Talk 02-09-2016
Effect of SBT Ferroelectric Layer on Polarity Controllable FETs for Improved Current Drivability Oral Presentation 14-12-2019
Enhanced Reliability of Polarity Controllable– Ferroelectric– FETs under the Impact of Fixed Trap Charges Oral Presentation 29-09-2019
Efficacy of Non-Uniformly Doped and Multi- layered Gate Dielectric Designs in Improving Device Perfomance of Elliptical MOSFETs Oral Presentation 20-09-2018
Design Space Optimization for Nanoscale Graded Channel Negative Capacitance (GCNC) SOI MOSFET for Improved Device Performance and Temperature Resilience Oral Presentation 16-11-2017
Analytical Model to Study the Impact of Ferroelectric Materials SBT/PZT on Elliptical Gate All Around Junctionless Transistor Oral Presentation 16-07-2017
Modeling and Analysis of Double Gate Ferroelectric Junctionless (DGFJL) Transistor Oral Presentation 23-09-2015
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